Taking a top-emission structure active matrix organic EL display as an example, a representative panel unit is formed by bonding together a TFT circuit substrate 11 on which is formed an organic EL element, and a color filter substrate 12, as shown in FIG. 1.
FIG. 2(a) is a schematic diagram of the wiring configuration of this TFT circuit substrate. In this TFT circuit substrate, there exist power supply lines 21 supplying a power supply (electric power) to the individual pixel circuits 24 arranged in one column, and a power supply bus 22 which combines all of these and leads them to a power supply terminal 23. Further, resin is provided to planarize the TFT depressions/protrusions, and normally contact holes 27 connecting emission portions are provided here. The numeral 25 denotes a data signal line, and the numeral 26 denotes a gate signal line.
FIG. 2(b) is a schematic diagram which extracts only this power supply-related wiring. In this way, a configuration of the power supply lines on the TFT circuit substrate in which lines run in one direction is used, rather than full-coverage wiring or a mesh shape. One objective of this is to prevent an increase in the capacitance between wires, and consequent slower driving, due to the increase in area of power supply lines traversing signal lines. A further aim, when pixels are small, is to increase the transistor area by even a small amount. The numeral 16 denotes the position of IC (control circuit) arrangement.
FIG. 3A shows a representative configuration of a pixel circuit. This is a TFT circuit used mainly with liquid crystal elements, but can of course also be used to drive organic EL elements. In this case the TFT-side power supply line is a cathode, and the common upper transparent electrode for all the pixels is a positive electrode. The numeral 31 denotes an organic EL element, 32 and 33 denote TFTs, 34 denotes a capacitor, 35 denotes a source signal line, and 36 denotes a gate signal line.
FIG. 3B is a schematic diagram showing one example of the wiring structure of a pixel circuit 24 of a conventional TFT circuit substrate. Here, the wiring structure is shown for the principle transistor forming the pixel circuit 24 of the conventional TFT circuit substrate.
In the wiring structure of FIG. 3B, a gate wiring pattern 55 is formed as a first-layer metal wiring pattern, and moreover a source wiring pattern 56, drain wiring pattern 57, and the power supply line 21 are each formed on the gate wiring pattern 55, with an insulating layer and a Si layer 29 interposed, as a second-layer metal wiring pattern.
A gate control element region 58 is provided adjacent to the gate wiring pattern 55. This gate control element region 58 is provided with the TFT (Thin Film Transistor) 33 and capacitor 34 shown in FIG. 3A, and moreover the data signal line (source signal line) 25 which is the second-layer metal wiring pattern, and the scan signal line (gate signal line) 26 which is the first-layer metal wiring pattern, are connected.
The source wiring pattern 56 is provided as wiring forming the source of the TFT 32 shown in FIG. 3A. The base portion of this source wiring pattern 56 is connected to the power supply line 21, and the tip portion is branched into a comb shape, to form branch portions 56a, 56b parallel to the power supply line 21.
On the other hand, the drain wiring pattern 57 is provided as wiring forming the drain of the TFT 32. The base portion of this drain wiring pattern 57 is connected to the light emission portion via the contact hole 27, and has a branch portion 57a extending from this base portion to between the branch portions 56a, 56b of the source wiring pattern 56, and a branch portion 57b extending from the base portion to between the branch portion 56b and the power supply line 21. That is, the drain wiring pattern 57 has comb-shape branch portions which mesh with the comb-shape branch portions of the source wiring pattern 56.
Next, a pixel portion of the panel of FIG. 1 has cross-sectional structures along lines AA and BB in FIG. 4A(a) such as shown for example in FIG. 4B(b) and FIG. 4C(c). First, on a glass substrate there exist a TFT structure and the planarization resin 40 for this. This may be covered with an inorganic passivation film as necessary. After depositing an underlayer 41 thereupon to improve closeness of contact, a reflective electrode 42 is formed. After forming an insulating film 43 having openings at emission portions, a plurality of organic films 44 are evaporation-deposited, and a transparent electrode layer 45 is deposited thereupon. Here, what is called the upper transparent electrode layer may be IZO, ITO, or another transparent oxide layer, or may be a half-mirror shape metal film of several nm to several tens of nm. This transparent electrode layer 45 is for example as shown in FIG. 5A(a) and FIG. 5B(b), and the full-coverage wiring 53 which is common to all pixels is connected at a panel peripheral portion to a power supply bus 51 separate from that above, and is drawn out to the terminal 52. And finally, the entire face of the pixel portion is covered by a barrier layer 46.
On the other hand, on the color filter substrate side, a black matrix 47, color filter 48, and also, if necessary, a bank barrier wall 39 and color conversion layer 49, are formed on a glass substrate. Of course, there are also methods in which a bank barrier wall and color conversion layer are not used. Also, spacers 50 may be provided as necessary.
And, the TFT circuit substrate and color filter substrate are positioned such that pixels are aligned, and are bonded together. In general, an adhesive or other solid is used as a gap layer, but a liquid or gas may be used.
On a TFT circuit substrate such as that of FIG. 2, thick-film wiring such as on a printed substrate is difficult, and so the wiring resistance cannot be ignored, and the voltage drop (rise) increases in moving away from the power supply terminal. In particular, in the case of a current driving method of self-emission such as an organic EL panel, the current flowing in the power supply lines is greater than for liquid crystal panels and similar, and the voltage drop (rise) at the power supply lines and power supply bus is greater. This leads directly to an in-plane distribution of the voltages across organic EL emission elements, resulting in brightness unevenness. Further, when a TFT pixel circuit is configured as in FIG. 3A, when the GND potential in particular rises, the gate control voltage fluctuates, and so extremely large brightness unevenness results even for a slight in-plane potential distribution. Further, in the case of a current driving method of self-emission such as an organic EL panel, the current flowing in power supply lines is greater than in liquid crystal panels and similar, so that the voltage drop (rise) at power supply lines and the power supply bus is greater. Hence only a small number of pixels near the power supply terminal where the GND potential is low are very bright, and if this is left unresolved and the average brightness for the overall panel is set, even screen burn-in may occur.
There have been various proposals, as follows, of methods to reduce brightness unevenness due to such potential unevenness near power supply wiring. Patent Reference 1, Patent Reference 2, and Patent Reference 3 attempt to reduce the wiring resistance (voltage drop) due to the power supply bus by supplying power to two or more places of the power supply bus itself. This is effective for reducing resistance. However, there are cases in which power cannot be supplied to a plurality of places due to problems of space and cost, and moreover if the screen is large and the current increases, the power supply bus cannot be made sufficiently thick, and in some cases, increasing the number of places of power supply to some extent does not adequately suppress the voltage drop of the power supply bus.
Further, in Patent Reference 4, Patent Reference 5, and Patent Reference 6 and similar, attempts are made to render uniform the potential on organic EL elements through contact hole wiring measures, and these are effective in cases in which potential unevenness on organic EL elements at the center of brightness unevenness is dominant. However, when using this method, no matter how the contact resistance is adjusted, the entire current is added to the common power supply bus and flows to the power supply terminal, so that a voltage drop always occurs across the power supply bus itself at a distance place from the terminal. That is, when applying this method, the distribution of the voltage drop of the power supply bus itself cannot be reduced, so that brightness unevenness caused by unevenness in the gate voltages of TFTs such as that of FIG. 3A cannot be reduced.
Patent Reference 7 discloses the reduction of variation in the potential of power supply lines by inserting one slit up to an intermediate position of the power supply bus. However, this one slit alone cannot adequately render potentials of power supply lines uniform when the number of power supply lines connected to the power supply bus is large or when the bus is long.
Patent Reference 8 discloses a substrate for displays which reduces voltage drops by connecting adjacent power supply lines (Vdd) at a plurality of places using metal lines. Here, reduction of the widths of the portions of intersection of metal lines and data lines to reduce parasitic capacitance is also described. However, in this configuration, power supply lines are simple connected in a mesh shape, so that for example during full-surface lighting, voltage drops are reduced prominently only near the power supply terminal, and concentrated brightness unevenness results.
It is also possible to correct the light emission instruction data itself sent to each pixel, to reduce brightness unevenness by software means. However, brightness unevenness in a screen is two-dimensional, and it would be necessary to provide memory sufficient for all pixels in the image controller and also set two-dimensional correction coefficients, entailing prohibitive costs.
Of course, power supply line materials can be changed to lower-resistance wiring materials, power supply line films can be made thicker, and bus widths can be expanded to lower power supply line resistances. However, a change in wiring material would necessitate changes in conventional processes, and thickening of power supply line films would cause cost increases and increases in internal stresses (warping, cracking, film peeling). Further, an increases in the bus width would cause an increase in the frame, and would further cause a cost increase due to the reduced product yield from the mother substrate.
Patent Reference 1: Japanese Patent Application Laid-open No. 2007-232795
Patent Reference 2: Japanese Patent Application Laid-open No. 2007-232796
Patent Reference 3: Japanese Patent Application Laid-open No. 2004-206055
Patent Reference 4: Japanese Patent Application Laid-open No. 2005-078071
Patent Reference 5: Japanese Patent Application Laid-open No. 2005-157300
Patent Reference 6: Japanese Patent Application Laid-open No. 2007-250553
Patent Reference 7: Japanese Patent Application Laid-open No. 2007-34278
Patent Reference 8: Japanese Patent Application Laid-open No. 2006-163384